Golovatyj А., Teslyuk V., Kryvyy R.

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Abstract. VHDL-Ams model of integrated membrane type micro-accelerometer with delta-sigma (ΔΣ) analog-to-digital converter for schematic design level was developed. It allows simulating movement of the sensitive element working weigh from the applied acceleration, differential capacitor and original signal capacity change, signal digitizing with the help of Delta- Sigma ADC with defined micro-accelerometer structural parameters, and analyzze an integrated device at the schemotechnical design level.

Key words: Micro-Electro-Mechanical Systems (MEMS), micromechanical sensitive element, integrated membrane micro-accelerometer, delta-sigma modulation, pulse-width modulation (PWM), delta-sigma analog-todigital converter (ADC), one bit digital-to-analog converter (DAC), VHDL-AMS hardware description language, hAMSter software, schemotechnical design level.

VHDL-Ams Model of the Integrated Membrane Micro-Accelerometer with Delta-Sigma (Δσ) Analog-To-Digital Converter for Schematic Design Level

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